Problem synthesizing Verilog created by Chisel

[dagema (Donnie Agema)]

@mwachs5

I also see that it is not finding the generated IP. You will need to generate the IP so you can use it (this is for the clock generation block and the System Reset block. In the freedom flow, this is done by a TCL script:

I set the system.v file to top, and worked out the right sequence for running the tcl scripts to get the ip generated, but I am still getting the “set_property” errors in the XDC contraint files: