How to add a general AXI device to the freedom project?

Hi,
I want to add a general AXI device to the freedom project. That is to say, the AXI device is a black box, which provides standard slave interface externally. I only need to connect it to the AXI bus and allocate an address space.Here, it is not necessary to assign interruption signals to the AXI equipment, and it is not necessary to generate the equipment tree in the DTS. The related codes are as follows:
1)fpga-shells\src\main\scala\devices\xilinx\xilinxadcvaramserdes\XilinxAdcvaRamSerDes.scala
case class AdcvaRamSerDesParams(baseAddress: BigInt)

class AdcvaRamSerDesPads extends AdcvaRamSerDesIO{
val I_tile_0_ref_clk_p = Input(Clock())
val I_tile_0_ref_clk_n = Input(Clock())
val I_tile_1_ref_clk_p = Input(Clock())
val I_tile_1_ref_clk_n = Input(Clock())
}

class AdcvaRamSerDes(c: AdcvaRamSerDesParams)(implicit p: Parameters, val crossing: ClockCrossingType = AsynchronousCrossing(8)) extends LazyModule with CrossesToOnlyOneClockDomain {
val adapter = LazyModule(new TLWidthWidget(8))
val frag = LazyModule(new TLFragmenter(4, p(CacheBlockBytes), holdFirstDeny = true))
val toaxi4 = LazyModule(new TLToAXI4(adapterName = Some(“ramserdes”)))
// val deint = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
val index = LazyModule(new AXI4IdIndexer(idBits = 0))
val yank = LazyModule(new AXI4UserYanker(capMaxFlight = Some(1)))
val buffer = LazyModule(new AXI4Buffer)

val axislavenode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = AddressSet.misaligned(c.baseAddress, 0x200000000L),
//resources = device.reg,
regionType = RegionType.UNCACHED,
executable = false,
supportsWrite = TransferSizes(1, 4),
supportsRead = TransferSizes(1, 4),
interleavedId = Some(0))),
beatBytes = 4)
))

this.crossAXI4In(axislavenode) := buffer.node := yank.node := toaxi4.node := frag.node := adapter.node
val node: TLInwardNode = adapter.node

lazy val module = new LazyModuleImp(this) {
// The IO definition is used in Shell.
val io = IO(new AdcvaRamSerDesIO {
val I_tile_0_ref_clk_p = Input(Clock())
val I_tile_0_ref_clk_n = Input(Clock())
val I_tile_1_ref_clk_p = Input(Clock())
val I_tile_1_ref_clk_n = Input(Clock())
val I_sys_rst = Input(Bool())
val I_sys_clk = Input(Clock())
})

val blackbox  = Module(new transceiver_8)

val (axi,_) = axislavenode.in(0)

// connect up IOs
// since we don't have a bajillion, we'll do it by hand
io.O_tile_txp_out              := blackbox.io.O_tile_txp_out
io.O_tile_txn_out              := blackbox.io.O_tile_txn_out
blackbox.io.I_tile_rxp_in := io.I_tile_rxp_in
blackbox.io.I_tile_rxn_in := io.I_tile_rxn_in

2)fpga-shells\src\main\scala\shell\RamSerDesOverlay.scala
abstract class RamSerDesOverlay(val params: RamSerDesOverlayParams)
extends IOOverlay[RamSerDesPads, ModuleValue[RamSerDesPCS]]
{
implicit val p = params.p

def ioFactory = new RamSerDesPads
val designOutput = InModuleBody { Wire(new RamSerDesPCS) }
}

3)fpga-shells\src\main\scala\shell\xilinx\AdcvaRamSerDesOverlay.scala
case class AxiRamSerDesOverlayParams(
address: BigInt,
wrangler: ClockAdapterNode,
corePLL: PLLNode)(
implicit val p: Parameters)

case object AxiRamSerDesOverlayKey extends FieldSeq[DesignOverlay[AxiRamSerDesOverlayParams, TLInwardNode]]

abstract class AdcvaXilinxRamSerDesOverlay[IO <: Data](val params: AxiRamSerDesOverlayParams)
extends IOOverlay[IO, TLInwardNode]
{
implicit val p = params.p
}

4)Codes added in the class DevKitFPGADesign:

p(AxiRamSerDesOverlayKey).headOption.map{
case e => { val ramSerDes = e(AxiRamSerDesOverlayParams(0x480000000L, wranglerNode(0), corePLL))
sbus.coupleFrom(“ram_bus”) { ramSerDes := TLWidthWidget(sbus.beatBytes) := _ }
}
}

Error occurs when compiling the verilog. The information is as follows:
[error] /freedom/src/main/scala/unleashed/DevKitFPGADesign.scala:173:90: overloaded method value := with alternatives:
[error] [EY](h: freechips.rocketchip.diplomacy.OutwardNodeHandle[freechips.rocketchip.tilelink.TLClientPortParameters,freechips.rocketchip.tilelink.TLManagerPortParameters,EY,freechips.rocketchip.tilelink.TLBundle])(implicit p: freechips.rocketchip.config.Parameters, implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo)freechips.rocketchip.diplomacy.NoHandle
[error] [DX, UX, EX, BX <: Chisel.Data, EY](h: freechips.rocketchip.diplomacy.NodeHandle[DX,UX,EX,BX,freechips.rocketchip.tilelink.TLClientPortParameters,freechips.rocketchip.tilelink.TLManagerPortParameters,EY,freechips.rocketchip.tilelink.TLBundle])(implicit p: freechips.rocketchip.config.Parameters, implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo)freechips.rocketchip.diplomacy.InwardNodeHandle[DX,UX,EX,BX]
[error] cannot be applied to (freechips.rocketchip.tilelink.TLInwardNode)
[error] sbus.coupleFrom(“ram_bus”) { ramSerDes :
= TLWidthWidget(sbus.beatBytes) :*= _ }
[error] ^
[error] one error found
[error] (Compile / compileIncremental) Compilation failed
[error] Total time: 6 s, completed 2020-3-26 15:20:25
common.mk:48: recipe for target ‘/freedom/builds/adcva-u500devkit/sifive.freedom.unleashed.DevKitU500FPGADesign_WithDevKit100MHz.fir’ failed

I modify the code to the following:
val SerDesRamOverlay = p(AxiRamSerDesOverlayKey)
if(SerDesRamOverlay.nonEmpty){
val ramSerDes = SerDesRamOverlay.headOption.map((AxiRamSerDesOverlayParams(0x480000000L, wranglerNode(0), corePLL)))
ramSerDes.zipWithIndex.map { case(ram, i) => {
val name = Some(s"ram
$i")
//sbus.fromMaster(name) { ram } // Master Read rocket bus
sbus.toFixedWidthSlave(name) { ram }
}
}}

There is still an error in compilation:
[error] /freedom/src/main/scala/unleashed/DevKitFPGADesign.scala:167:38: type mismatch;
[error] found : freechips.rocketchip.tilelink.TLInwardNode
[error] (which expands to) freechips.rocketchip.diplomacy.InwardNodeHandle[freechips.rocketchip.tilelink.TLClientPortParameters,freechips.rocketchip.tilelink.TLManagerPortParameters,freechips.rocketchip.tilelink.TLEdgeIn,freechips.rocketchip.tilelink.TLBundle]
[error] required: freechips.rocketchip.diplomacy.NodeHandle[freechips.rocketchip.tilelink.TLClientPortParameters,freechips.rocketchip.tilelink.TLManagerPortParameters,freechips.rocketchip.tilelink.TLEdgeIn,freechips.rocketchip.tilelink.TLBundle,?,?,?,?]
[error] sbus.toFixedWidthSlave(name) { ram }
[error] ^
[error] one error found
[error] (Compile / compileIncremental) Compilation failed
[error] Total time: 6 s, completed 2020-3-26 16:44:39

In this case, there is no need for interruption. How to connect to the AXI bus as a general AXI equipment?
Thank you very much!