Connect custom IP to AXI


(Dominic) #1

Hi,
My aim is to activate an AXI Master Port to add custom periphery IPs. I added “CanHaveMasterAXI4MMIOPort” and “CanHaveMasterAXI4MMIOPortModuleImp” to “class E300ArtyDevKitSystem” and built the veriolog.
Now I can see the modules like “AXI4Buffer”, “AXI4UserYanker”… in my verilog file, but I am not able to find suitable ports I could connect to in Vivado.
I also tried to understand how the Xilinx MIG is ported as a Blackbox in the VC707 config, but was not able to take over the right code sections because I am completely new to scala.

I am reading these scala files for weeks now and was not able to come up with a solution.
Has anybody done that using the freedom repo and could help me?


Thanks in advance


(Boran Car) #2

Could you tell me more about your total flow - do you use Chisel3 and FIRRTL to generate the final verilog toplevel or just a wrapper that you use in your toplevel?

Since you’re using the E300ArtyDevKitSystem, I’m assuming you’re going with Chisel3 and FIRRTL generating your toplevel, in that case I’d recommend using Diplomacy to adapt TL from Rocket to your AXI. You need to write an AXI wrapper around your AXI powered blackbox. I found the sifive/nvidia-dla-blocks NVDLA.scala quite a useful example to start from. Take some time understanding how to connect it to sbus, again, look at Periphery.scala from that same repo (note that you don’t need fbus, just sbus).

If you’re not using Chisel3 + FIRRTL for your toplevel, note that Chisel3 and/or FIRRTL will remove any unused pins and as a result you may get some modules removed, too. You need to either expose them at the generated toplevel or instruct the pipeline not to remove them.


(Dominic) #3

First of all, thank you for your response.
I kind of tried both. My aim was to use the Chisel3/FIRRTL by writing a wrapper similarly to the one Xilinx MIG. There were numerous errors and I thought it might be faster/easier to simply activate the MasterAXI4MMIOPort and add my AXI Slave using Vivado than becoming a scala expert.

You need to either expose them at the generated toplevel or instruct the pipeline not to remove them.

I added “dontTouch(mmio_axi4)” to Ports.scala, but did not see a change in the .v

I will try to fix my wrapper :exploding_head: