My aim is to activate an AXI Master Port to add custom periphery IPs. I added “CanHaveMasterAXI4MMIOPort” and “CanHaveMasterAXI4MMIOPortModuleImp” to “class E300ArtyDevKitSystem” and built the veriolog.
Now I can see the modules like “AXI4Buffer”, “AXI4UserYanker”… in my verilog file, but I am not able to find suitable ports I could connect to in Vivado.
I also tried to understand how the Xilinx MIG is ported as a Blackbox in the VC707 config, but was not able to take over the right code sections because I am completely new to scala.
I am reading these scala files for weeks now and was not able to come up with a solution.
Has anybody done that using the freedom repo and could help me?
Thanks in advance