Chisel help for connecting IO to black-box module


I’m trying to make an addition to the unleashed + vcu118 setup which includes a black-box verilog module instantiation (very similar to the nvdla configuration).
Can someone direct me about how to connect some FPGA pins (specifically the PMOD IO defined as FPGAJTAGIO module) to some ports at the black-box module instantiated at src/main/scala/unleashed/IOFPGADesign.scala file?


PS I am looking for a consultant who can help with questions like this.

(Boran Car) #2

You can check how I’ve added ports for the Xilinx EthernetLite at the top level of the Everywhere Arty in this commit - Feel free to browse the sources in general

P.S. Feel free to DM me if you’d like.