I’m trying to make an addition to the unleashed + vcu118 setup which includes a black-box verilog module instantiation (very similar to the nvdla configuration).
Can someone direct me about how to connect some FPGA pins (specifically the PMOD IO defined as FPGAJTAGIO module) to some ports at the black-box module instantiated at src/main/scala/unleashed/IOFPGADesign.scala file?
Thanks
PS I am looking for a consultant who can help with questions like this.