Hello.
Is there an easy way to add a tlck module and connect it to the uart module so that the line with clocks appears in dts?
L18: serial @ 64000000 {
clocks = <& L17>;
compatible = “sifive, uart0”;
I would like to avoid using a lot of additional classes like in the u500.
Figured out.
Need to add in class E300ArtyDevKitSystem instead HasPeripheryUART:
val tlclock = new FixedClockResource(“tlclk”, p(DevKitFPGAFrequencyKey))
val uart = p(PeripheryUARTKey).map { ps =>
val divinit = (p(PeripheryBusKey).frequency / 115200).toInt
val u = UART.attach(UARTAttachParams(ps, divinit, pbus, ibus.fromAsync))
tlclock.bind(u.device)
u
}
val uartNodes = uart.map { u =>
u.ioNode.makeSink
}
Add in class E300ArtyDevKitSystemModule instead HasPeripheryUARTModuleImp :
val uart = outer.uartNodes.zipWithIndex.map { case(n,i) => n.makeIO()(ValName(s"uart_$i")) }
Add in file System.scala
case object DevKitFPGAFrequencyKey extends Field[Double](100.0)