Hi,
I am trying to configure the UART with baud rate 115200 at power reset, the tlclk is 13.8 MHz.
What value should be set to UART divisor register to achieve 115200 baud rate ?
Calculation yields divisor to be 12 as (13.8 MHz / 115200).
Also, is there a pin on board to probe this tlclk?
Hi @bsvtgc how did you get your value of 12? I calculate the divisor as 13,800,000 Hz / 115,200 bps = 119 (truncated, rounded down).
Note that the value you store in the DIV field of register offset 0x18 is one less than this calculated value, in other words, 118 in this case of the 13.8 MHz clock rate.
See Section 18.9 in the Freedom E310 Manual
To probe the internal tlclk (or, hfclk) signal at the outside world, you can configure and enable any one of the three PWM blocks, and look at the PWMx.0 pin of that block.
@pds Thanks for your reply.
with my eyes wide open now, I don’t know how I arrived at value 12.
For hfclk probe, let me try with PWM.