Hi @bsvtgc how did you get your value of 12? I calculate the divisor as 13,800,000 Hz / 115,200 bps = 119 (truncated, rounded down).
Note that the value you store in the DIV field of register offset 0x18 is one less than this calculated value, in other words, 118 in this case of the 13.8 MHz clock rate.
To probe the internal tlclk (or, hfclk) signal at the outside world, you can configure and enable any one of the three PWM blocks, and look at the PWMx.0 pin of that block.