I am working to port freedom e300 to the arty s7 , so far i have been able to change what I think is necessary, xdc and tcl config files, only thing is a problem with QSPI clock . On Arty, freedom uses the additional pin connection to QSPI clock pin to drive the clock , this is not possible on Arty S7.
I have done a few attempts described here https://github.com/sifive/freedom/issues/46
but still not been able to boot, and actually I have some timing problems.
Does someone from freedom experts tell me what am I missing please.
Hi,
I can’t help you with the freedom RTL specificly because I‘m not familiar with it. But to access the SPI clk signal on the Arty S7 you must instantiate the Xilinx “startupe2” primitive in the verilog code. This allows access to the configuration clock. I haven’t tried it on my own yet, but to my understanding you must connect the spi clk output of the freedom RTL to the usrcclk0 input of the primitive.
Alternatively you can buy a PmodSF3 from Digilent and connect it to some of the pmod connectors. The SF3 contains a SPI flash chip similar to the one soldered on the board but you will have complete control over it. Of course it is not a out-of-the-box solution, but it may be a good starting point. You only need to adapt the xdc file to connect to the Pmod.