Memory map for RV32


Can someone please help me in understanding the memory map for the RV32 core.
I have generated a version of the core with the JTAG mdoule which has ExtMemSize set to 0x2000000L.
When I look at the memory map generated I see the memory has increased to the value I want.
However I do not see any explicit memory region for the Debug Ram and Rom. Is this because it is always fixed?
I have a system when we ask (via the JTAG) the Debug Module how much memory it has it comes back with the value 7 words (i.e. 28 bytes). Is this correct?
When the Debug Module is instantiated it has a value of 64 passed to it but in the body of the Debug Module code (Debug.scala) there is a comment that says ‘This code assumes only 28 bytes of Debug RAM’. Will it always be fixed or will be possible to increase this?

Thanks in advance,

1 Like


Just to be clear, the RISC-V architecture doesn’t define a memory map. At SiFive, we are defining the Freedom Platform, which includes the memory map, so my answers apply to that.

The Debug RAM and ROM region is indeed fixed, so that the Debug Region starts at 0x00000000. The debug RAM and Debug ROM offsets are as specified in the current version of SiFive RISC-V debug standard, which you can find here:

For a core generated by the rocket-chip generator, we use the minimum amount of Debug RAM (to save area). So for a RV32, that is 28 bytes and your JTAG connection seems to be functioning properly. It is higher if you instantiate a RV64 core. The standard allows debug RAM to be increased to 64 bytes, so you could create a rocket-chip config with a DMKey that sets the amount of debug RAM up to 64 ytes (The standard allows it to go even higher, but the rocket-chip generator doesn’t support this option at the moment).

The comment that says “this code assumes only 28 bytes of Debug RAM” means that that version of the Debug ROM code only needs 28 bytes of Debug RAM to function properly. You could add more if you have ideas about how to use it.

Thanks for that. Yes, I did mean to say my questions way related to the rocket-chip generator.
Yes, I am familiar with the debug spec, in fact I have provided feedback to Tim.
My questions and mis-understandings are from the rocket-chip view. For example I had expected the Debug memory map to be in the overall memory map output, but then again if it is fixed one could argue it doesn’t need to be there. I just think it would have been more complete.

I have just added a line in my specific config to set the DMKey to something larger and it appears to have done it.

Gosh, I am really impressed!! (Not with me you understand, but, with the power of the generator).

We will stick with the 28 bytes for now before baking another FPGA, just in case we need other changes.

Thanks again,