RISC-V External Debug Version 0.13: Program Buffer

Archive SiFive RISC-V Core IP Evaluation
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Hi All,

  1. Is there any specific PC address specified for Program Buffer start address from Processor point of view like v0.11 (0x800). If not what is the expectation of the spec.

  2. Program buffer ends with EBreak. But to go back to main program it is required to execute dret instruction right. Can anyone provide sequence.

Thanks & Regards,
Leela Krishna.

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  1. The specification (v13) doesn’t define one, since the debugger does not need to know it. It is only required that the processor “halt” when halt is requested by the debugger.

In practice, both Spike and rocket-chip interpret the halt request as an interrupt and jump to a Debug ROM location in order to halt. The Debug ROM happens to be at 0x800. But again this is not part of the Debug Specification. For reference, you can see the Debug ROM contents here: https://github.com/riscv/riscv-isa-sim/blob/master/debug_rom/debug_rom.S

  1. The ebreak that ends the program buffer is not the same as a dret, because the Core stays in Debug Mode when hitting the ebreak. The debugger never needs to know about or write a dret into the program buffer, the debug module will cause one to be executed when debugger does “resume request”.

Again you can see how this actually happens in the Debug ROM above, but the debugger should not need to write dret.

These are two major differences between v11 and v13 debug spec.