Which test-program could be used in RTL simulation?

Archive SiFive RISC-V Core IP Evaluation
1

Hi!
I have downloaded sifive_coreip_E24_AHB_rtl_eval_v19_05p1_release from your website, and I want to do some RTL simulations. I run make TARGET=design-rtl PROGRAM=dhrystone CONFIGURATION=release software in freedom-e-sdk. But it returned:

dhrystone section '.text' will not fit in region 'flash'
dhrystone section '.bss' will not fit in region 'ram'
region 'flash' overflowed by 12744 bytes
region 'ram' overflowed by 4224 bytes

It seems that the LENGTH of flash and ram in freedom-e-sdk/bsp/design-rtl/metal.ramrodata.lds is too small:
image

Is it OK for me to change it to a larger value for RTL simulation?

1 Like
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I have been following the Rapid Embedded Prototyping with SiFive Software webinar SiFive did recently and got stuck with the RTL build failing like you describe.

Did changing the length solve the problem for you?

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May I know what program are you using to evaluate the RTL? I’m just new to evaluating RTLs…