About benchmark compile environment for E31 evaluation

Hi, I’d like to evaluate the performance of E31 through simulation based on evaluation RTL…

In my understanding, the benchmark needs to be compiled with crt.S, syscalls.c or something else.
When I referred ‘github.com/sifive/freedom-e-sdk’, the compile script for coreip-E31 seems to be under construction. (just hello.c can only be compiled…)

Is there a guideline to compile benchmarks (e.g., dhrystone, coremark) for E31 evaluation? (not for the FPGA)
or, can I get some benchmark binaries (much more complicated than basic applications such as add, mul, …)

Thank you.

freedom-e-sdk is in the middle of a major rewrite. I’d suggest checking out the last commit before the rewrite started, which is the commit from September.

I’ve made a branch v1_0 at that commit.

I suggest most people check that out rather than master.

It might even be a good idea to make it the default branch, but I can’t do that on that repo.

Thanks Jim and Bruce.

As suggested, I find the branch v1.0 of freedom-e-sdk.
However, it seems that the branch does not include the compile environment for E31 bare metal (bsp option=coreip-e31).
Is it possible to run E31 RTL simulation with a hex file which is compiled with bsp option=freedom-e300-hifive1 ?

I don’t know how RTL simulation works. Benchmarks like dhrystone and coremark will try to print a result at the end, and printing can only work if you have a UART, an appropriate driver for that UART, and appropriate emulation support for that UART. Arty and e300 may have different UARTs. For RTL simulation of a core, you may not have any UART at all. But maybe if you generate a log from simulation, and you can see the register values, maybe you can find the values that would have been printed at the end in the simulation log.

FYI This pull request
was an attempt to get things building again on mainline with the mee support, but a lot of stuff has changed since then so I don’t know if it is still useful.