Obfuscated simulation output

Archive SiFive RISC-V Core IP Evaluation
1

Hi, I have evaluated E31 core ip using RTL v19.02.

According to the evaluation guide, ‘make all-waves’ command can be successfully executed with VCS tool.
However, in the ‘.out’ file, all the output is ‘obfuscated simulation output’. In the eval guide document, it should be printed like below

C0: 483 [1] pc=[00000002138] W[r 3=000000007fff7fff][1] R[r 1=000000007fffffff] R[r 2=ffffffffffff8000]
C0: 484 [1] pc=[0000000213c] W[r29=000000007fff8000][1] R[r31=ffffffff80007ffe] R[r31=0000000000000005]
C0: 485 [0] pc=[00000002140] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r 0=0000000000000000]

I didn’t modify any things from the provided files. Could anyone please verify the evaluation RTL and evaluation results using rv32ui-add and rv32um-mul? I don’t know why I can’t get normal outputs…

Thanks

2

In the “SiFive E31 Core Complex Evaluation User Guide”, section 1.3, “Evaluation Version Limitations”, the fifth bullet item is “The testbench instruction trace output is obfuscated.”. That seems to cover what you are asking about. Presumably if you want unobfuscated output, you have to license it, but I’m not a hardware engineer so I don’t know the details.

If you want a fully free core, you could look at sifive/freedom on github or the Berkeley freechipsproject/rocket-chip.

3

Ah… I understood. I missed the evaluation limitations… Thanks for your quick response!