Is it possible to have larger I/D cache and I/D TIM in core IP?

Based on core IP, E31/E51 can have up to16KB I-Cache or 8KB ITIM, 64KB DTIM. U54 core does not seem to have TIM. Our existing design uses ARM M-/R- processor with larger I/D cache ~32K each and TCM(similiar to DTIM) ~128KB each… Is it possible to support larger cache and TIM ? We can run core at lower frequency ~800MHz. Thanks.

Hi there, yes it is possible to configure the I-Cache and DTIM sizes for our cores. The evaluations available for download represent specific implementations and hence the fixed memory sizes.

I’ll PM you as we are very interested in learning more about your requirements.