Error in downloading the vcu118 bitstream by vivado 2018.2


(ZhuXuanlong) #1

Hi,
The vivado version of my compilation environment is 2018.2, and compile the vcu118 with Makefile.vcu118-u500devkit. The following error occurred during downloading bitstream with vivado:

open_hw_target
current_hw_device [get_hw_devices xcvu9p_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xcvu9p_0] 0]
INFO: [Labtools 27-1434] Device xcvu9p (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
**Resolution: **
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use ‘get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]’.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
set_property PROBES.FILE {} [get_hw_devices xcvu9p_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xcvu9p_0]
set_property PROGRAM.FILE {/freedom/builds/vcu118-u500devkit/obj/VCU118Shell.bit} [get_hw_devices xcvu9p_0]
program_hw_devices [get_hw_devices xcvu9p_0]
ERROR: [Labtools 27-3303] Incorrect bitstream assigned to device. Bitstream was generated for part xcvu9p-flga2104-2L-e, target device (with IDCODE revision 0) is compatible with es1 revision bitstreams.
To allow the bitstream to be programmed to the device, use “set_param xicom.use_bitstream_version_check false” tcl command.
INFO: [Labtools 27-3164] End of startup status: HIGH
ERROR: [Common 17-39] ‘program_hw_devices’ failed due to earlier errors.

According to the prompt, no more errors will occur after executing the following statement, but an warning will occur:
set_param xicom.use_bitstream_version_check false
0
set_property PROBES.FILE {} [get_hw_devices xcvu9p_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xcvu9p_0]
set_property PROGRAM.FILE {/freedom/builds/vcu118-u500devkit/obj/VCU118Shell.bit} [get_hw_devices xcvu9p_0]
program_hw_devices [get_hw_devices xcvu9p_0]
WARNING: [Xicom 50-99] Incorrect bitstream assigned to device. Bitstream was generated for part xcvu9p-flga2104-2L-e, target device (with IDCODE revision 0) is compatible with es1 revision bitstreams.
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 6895.848 ; gain = 0.000 ; free physical = 378710 ; free virtual = 773686
refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0]
WARNING: [Labtools 27-3089] Calibration is still in-progress.
INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 MIG core(s).
INFO: [Labtools 27-3143] Calibration status change detected, refreshing MIG_1

Is this vivado version incompatible with freedom or something else?


(ZhuXuanlong) #2

I have contacted the FAE of Xilinx. Because the FPGA on vcu118 development board is an ES1, that is, engineering sample.