[Doc] Port Property of the GbE subsystem architecture

HiFive Unmatched
1

In SiFive FU740-C000 Manual v1p3 page 132, Figure 39.
GEMGXL Master interface connects to a TileLink Slave port.

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However, in the top-level block diagram, this port is connected to a TileLink Master Port.

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Is this a typo, or am I misunderstanding?

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