My name is Yunhao and I am teaching CS4411/5411 (operating systems practicum) at Cornell using SiFive technology. Specifically, I am running the SiFive freedom fe310 on the Arty FPGA; and run an OS on top of it.
Currently, freedom uses the tiny config of rocket-chip which disables virtual memory: the “useVM” field is false here: rocket-chip/Configs.scala at b21c7879b3ea22f69cb8457109561f37c225f8ea · chipsalliance/rocket-chip · GitHub
I tried to set “useVM” to true and recompile the CPU, but compilation fails due to the TestGeneration in this file: rocket-chip/Generator.scala at b21c7879b3ea22f69cb8457109561f37c225f8ea · chipsalliance/rocket-chip · GitHub
Are there any hints of how I may compile freedom fe310 with useVM enabled? I plan to dig deeper into the repo myself as well, especially the TLB and PTW components of rocket.
Enabling virtual memory translation will not only benefit my project, but also many students in terms of learning operating systems.