Modifying U500 in VCU118


I’m working on the project to make tape-out with freedom U500 model in
GitHub - sifive/freedom: Source files for SiFive's Freedom platforms.
For test and verification, I’m going to use VCU118 board.

To do so, I need to

  1. Replace the BootROM in the model with RAM which can be accessed by out of chip with communication module(UART).
  2. Replace the cache block with SRAM which supported by the fab company.

For #1,
when I follow the instruction in the github with the command,
$make MODEL=VC707BaseShell -f Makefile.vcu118-u500devkit verilog
$make MODEL=VC707BaseShell -f Makefile.vcu118-u500devkit mcs
I understand the simply workflow of generating mcs file (scala files → .fir ->verilog ->.mcs)

I’m trying to replace the BootROM by modifying sifive.freedom.unleashed.DevKitU500FPGADesign_WithDevKit100MHz.v file.
But I’m pretty sure that other works are needed to change I/O pin configuration for UART to connect my computer to BootROM. What other files should I change?

For #2,
when I check the icache and dcache in sifive.freedom.unleashed.DevKitU500FPGADesign_WithDevKit100MHz.v file,
these are not in the form of memory interface that i expected(such as modules with addr, data, cen, wen …)

So I cannot simple replace it with SRAM. In the scala file or .fir file, is there any option that I can generate verilog file with cache which is in memory interface?

Any advice will be very helpful for me!

plz reply!

thank you.

SiFive isn’t maintaining this freedom platforms repo anymore. It has been archived. I would suggest looking at Chips Alliance which owns the rocket chip generator now.