Hi all,
I’ve been porting MicroPython to the SAMD21 for Adafruit (we’re calling it CircuitPython to avoid confusion.) The SAMD21 has 32k ram which has been kind of a tight fit. I’d love to port to the E310 but worry about the 16k of data ram. I’m curious. Why does the chip have 16k data ram? Is it a die space issue?
Keep up the good work! I can’t wait to get my hands on a HiFive.
~Scott
Sounds like a very cool project. We’d be happy to answer any questions that could help your effort!
To understand the area impact of the RAM, check out the die plot of the FE310 in the slides from the last RISC-V workshop (Slide #8): https://riscv.org/wp-content/uploads/2016/12/Tue0930-FE310_HiFive1_v2-Kang-SiFive.pdf
16kB data RAM is sufficient for many applications (SW would always happily accept more!). Notably for the SAMD, 32kB is the highest range of that family.
The open source repo makes it really easy to tweak the size of memories, so anyone is encouraged to tweak the RAM sizes to explore the feasibility & performance of their SW given different design points.
Ok, thanks! I’ll keep that in mind.
That die plot is really cool! It appears that it would run out of space with more RAM. I’ll give it a shot anyway once I get my FPGA going as an E310. I’m currently hung up on getting Vivado going in a VM on Mac OSX.
I realize 32k is the limit for the SAMD21 and would love it if Atmel made a larger version. 
I love how your core is open source and I fully intend on experimenting with RAM sizes on the FPGA. I was also thinking about accelerators that would make it better too. (Maybe a neopixel peripheral.)
NeoPixel peripheral would be awesome!!