fRISCy: New high-performance PCB coming with FE310 + FPGA suitable for development or production systems

Hi everyone,

I hope this is an appropriate place to announce a forthcoming circuit assembly that I’m very excited to share. I’ve been intrigued by RISC-V, and after SiFive sent me a few samples of the FE310, I had to put it into a hobby project. I’m days away from sending the first revision to fabrication, and after hearing the Spark Gap podcast mention the FE310, I knew I had to share it somewhere. The board is named “fRISCy” (for FPGA + RISC-V) and I think it would be suitable for development or hopefully even inclusion in an industrial embedded system somewhere. In addition to the FE310, I’ve added an FPGA and the new SYZYGY carrier-side connector. I envision this board being at the heart of systems such as SDRs, sensor arrays, industrial controls, etc. I’m not entirely sure what method I’ll use for distribution, but I’ll try to put updates in this thread. Once I go to fab, I’ll have some time to set up a website and post preliminary documentation which I’ll link to here as well. (No promises on being quick… I still have a full-time job and 3 kids, so I only have a few hours per week to work on hobby projects) Here’s a list of some key features - I appreciate any feedback you guys might have. Thanks!

  • SiFive FE310 RISC-V Microcontroller with 128Mbit QSPI Flash memory
  • Xilinx Artix-7 FPGA with SYZYGY Standard carrier-side connector (footprint compatible from XC7A15T to XC7A100T)
  • R-pi form factor including 40-pin GPIO header, RJ-45, and USB Micro-B
  • 10/100 Ethernet PHY and 4Mbit SRAM connected via FPGA
  • SPI + GPIO interface between FE310 and FPGA for bidirectional data transfer


Which Artix-7 FPGA will you be using?

That’s a very nice looking board! I’m looking forward to more RISC-V + FPGA mashups.

In this case (fRISCy) we have a very open MCU, with a relatively closed FPGA (Xilinx). In the case of the BlackIce we have a closed MCU (STMF103) with an FPGA (Lattice iCE40HX4K) that has a fully open reversed-engineered toolchain.

All we need now is for someone to mate the open RISC-V with the reversed-engineered iCE40 :slight_smile:

Looks great! The SiFive team will be eager to see your updates, and you should come visit us if you’re ever in the area.

Hey guys,

@dagema, I’ve designed for the XC7A15T in the FTG256 package (so no transceivers). It’s footprint compatible up to the XC7A100T, though the limiting factor might be the power supply. I’ve only got 2A available on the VCCINT rail, and 2A for the VCCAUX.

@twoerner, thanks! I did consider the Lattice parts; I’ve had lots of good experiences with them recently. Ultimately, though, I’m just more familiar with the 7-series, and using one of them means less documentation I had to read :). I also want to squeeze as much performance as possible from the SYZYGY interface.

@allenl, thank you!

Is the top right connector the standard JTAG?

Looks cool. I would be interested in it. Any chance to buy one somewhere in the future? Will it have usb-jtag on board? And if yes, will it support also programming the FPGA?


Hey guys,

@ilg, yes that’s the FPGA’s JTAG, standard Xilinx pinout.

@thornschuh, it does have USB-JTAG for the E310 (+UART). I really wanted to put the FPGA on the same JTAG chain but it looks like Vivado will only recognize authorized cables so I went with their JTAG connector to be safe. You’ll definitely be able to purchase it at some point, though I haven’t figured out what method I’ll use for distribution.

Ah, so it’s not connected to the FE310?

Although this is the solution used on the HiFive1 board, if you plan to do any software development on the board, you’ll probably want to use a serious JTAG probe, and this will require a JTAG connector. It can be the small JTAG, not the large one.

The FTDI solution requires OpenOCD, which is very unstable, almost unusable.

For any serious development, the SEGGER J-Link (EDU) is much faster and by far more stable. Highly recommended!

Yep, there are 2 completely separate jtag chains. As for the E310 jtag, I did bring it out to an 0.050" header for connection to a different debugger. When I get around to making a web page for the board I’ll post a proper block diagram too.

Hi All,

I’ve created a reasonable system block diagram (sorry, the power supply system is not documented here). Next step will be a web-page for the board, followed by a decision on how to manufacture and distribute.


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If you connect the FE310 JTAG both to the FTDI and the external header, you must be sure you avoid conflicts. If all FTDI outputs are open collector and the chip is not active, it should be fine, otherwise you probably need some jumpers to disconnect the wires from FTDI.

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