Hi, I am wondering if there is any information available on the sort of costs involved in bringing chips like the SI-Five1 and Unlimited from draft to market? Maybe an informational article even? Not talking quotations or anything binding or even that precise, just a general overall view.
Thanks 
Hi, this is quite a complicated area, one in which we have actually gotten requests for help on from industry analysts to help tackle.
At SiFive, we think that as part of the RISC-V revolution will be the ability to bring these costs down dramatically so that more companies, more folks, and more projects can happen.
This article has some industry numbers which may give you some good guidance:
It’a hard to make sense of these numbers.
For example, the article says $30 million to develop a 28nm chip.
First, surely it depends on how complex and how large the chip is. A chip consisting mostly of a Rocket core is going to be a very different cost to a Core i7, and a chip consisting almost entirely of SRAM different again.
Second, public press releases show that, as of about a year ago, SiFive has had $8.5m of funding, and yet has produced two chips, including a quad core 1.5 GHz one comparable to something like ARM A53 at 28nm.
Obviously, something doesn’t line up here.
Maybe one big factor is the difference between automatic and hand layout of the chip.
I noted a year ago that 320 MHz for the HiFive1’s FE310-G000 in 180nm is pretty good compared to most ARM chips topping out at 180 MHz in that process. However, back when Intel and Motorola were using 180nm for their flagship chips, they had both Pentium 3 and PowerPC G4 at 1.0 - 1.2 GHz. No doubt they spent an absolute fortune on manual layout and optimising pipeline stages in achieving that.
Unfortunately, there are far too many variables to be able to give a simple answer. The cost of bringing a 28nm chip to market can easily vary over two orders of magnitude (e.g., $2M-$200M) depending on what you’re building. At SiFive, we are working to bring these costs down but there will always be a wide range.
Imagine asking someone how much does it cost to bring a piece of software to market. There’s a big difference between a flashlight app for the iPhone and something like MS Office.
Even Intel has mostly abandoned hand-drawn manual layout, outside of memories. There are too many difficult constraints and too few good designers to support this level of customization these days. Also, when looking back at old 180nm custom designs it is important to remember that not all 180nm processes are created equal: 180nm processes tuned for synthesis are generally going to be slower, but denser and lower power, than 180nm processes tuned for custom processor designs.
I thought by now 675mm wafers would be the norm and hence cut down on price. Alas a bit of reading suggests the cost savings are not that great. My thinking is that the region between 28nm-5nm is forcing innovation on the fabrication process to find way’s of reducing cost not just scaling down. We’ll be stuck at these technology nodes for a while so efficiencies in costing and competitive markets means the pressure is to expand capacity as demand rises with it. The race is no longer about scaling down the technology but scaling up the production line as more foundries get requests for a technology node no longer shrinking as fast.
I’m totally speculating here but I think soon there will be a drive to have an open library for technologies for prototyping at the 90nm node and greater range as more commercial demand goes towards the smaller nodes less than 45nm. The offshoots for this are already in the making and the RISC-V ISA is one of those drivers; I just wonder what more can be done to partner with foundries to this end?