I’m looking for a way to trigger an interrupt when something is received through UART.
Documents on the SiFive FE310 looked incredibly promising, but lacking information. SiFive FE310-G000 Manual v3p1, Section 17.8, “Interrupt Registers (ip and ie)” says:
“The rxwm condition becomes raised when the number of entries in the receive FIFO is strictly greater than the count specified by the rxcnt field of the rxctrl register”
After reading the whole chapter a couple of times, I still don’t see how to use it to enable and then to trap UART exceptions.
Please, has anyone done something similar?
I could successfully poll the UART Interrupt Pending Register, after what I go read the rxfifo. But polling is far from interrupt handling, so I’m still looking for what is promised on the document.