.equ AONBASE, 0x10000000
.equ rtccfg, 0x040
.equ rtccountlo, 0x048
.equ rtccounthi, 0x04C
.equ rtcs, 0x050
.equ rtccmp0, 0x060
.globl _set_rccmp
_set_rccmp:
li t0, AONBASE # loads the AON base address
lw t1, rtccfg(t0) # loads the config address which is rtcscale
ori t2, t1, 15 # andi the rtcscale to seconds in t1.
sw t1, rtccfg(t0) # store the new rtcscale
lw t1, rtcs(t0) # loads the current clock time
addi t1, t1, 0x03 # adds 3 seconds to the current clock time
sw t1, rtccmp0(t0) # sets the time to compare 3 seconds higher
I have this code, but reading the documentation on 16.3 of the SiFive FE310-G002 Manual v19p04
It says that it only sets the interrupt pending bit on rtccmpip.
Here is my mtvec initialization that I would guess would be triggered after 3 seconds.
_set_mtvec:
csrrci t0, mstatus, 3 # disable interrupts
la a0, _fail_handler # loads fail handler
csrrw t2, mtvec, a0 # get address of fail handler
csrrci t1, mtvec, 1 # set to direct mode
csrrsi t0, mstatus, 3 # enable interrupts
ret
.align 8
_fail_handler:
...
With a breakpoint on my _fail_handler I never see it hit.
Is there another way to trap rtc interrupts I might be missing?