How to enable UART1 RX watermark interrupt alone?

HiFive1 Rev B
1

Here is what I observe:

Enabled UART1 receive watermark interrupt ONLY.

(gdb) x 0x10023010  -> UART1 interrupt enable register address
0x10023010:     0x00000002 -> bit[1] -> Receive watermark interrupt enable bit

When UART1 interrupt occurs, inspection of UART1 interrupt pending register reveals that both rx & tx watermark interrupts pending.

(gdb) x 0x10023014  -> UART1 interrupt pending register 
0x10023014:     0x00000003  -> bit[0] - txwm, bit[1] - rxwm interrupt pending bits

is this expected?
I would expect only the rx watermark interrupt pending (when tx watermark interrupt isn’t enabled)

2

The interrupt pending bits in register IP reflect the local status of the device block; they are always active. The interrupt enable bits in register IE control whether the IP’s status bit(s) are passed through to the higher level PLIC; IE thus gates the IP bits like txwm and rxwm. If you don’t wish to see any txwm status, you can always set its level to a high value, such as txcnt=7.

For example, my lowest level void uart_write(uint8_t x) primitive is:

while( uart_tx_full() );
uart_tx_data( x );

And my lowest level uint8_t read() primitive is:

while( uart_ip_rxwm() == 0 );  /*wait for char (blocking read)*/
return uart_rx_data();