The interrupt pending bits in register IP reflect the local status of the device block; they are always active. The interrupt enable bits in register IE control whether the IP’s status bit(s) are passed through to the higher level PLIC; IE thus gates the IP bits like txwm and rxwm. If you don’t wish to see any txwm status, you can always set its level to a high value, such as txcnt=7.
For example, my lowest level void uart_write(uint8_t x) primitive is: