Is interrupt vectoring available in HiFive1?

HiFive1 Rev B
1

Hello,
I am trying to enable interrupt vectoring in HiFive1 board. I do:
csrwi mtvec, 1
csrwi mtvec, some_address
csrwi mstatus, 8
csrwi mie, 8

li t0, 1
li t1, 0x02000000
sw t0, 0(t1)

And I thought that the software interrupt should be generated but it is not generated.
So I have no ability to check whether vectoring works.
What am I doing wrong? or how can I generate a software interrupt?

2

Denis,

The HiFive1 does support software interrupt. It does not support “vector” mode interrupts (with LSB of mtvec != 2’b00).

Some notes about your code:

  1. What is the purpose of your first instruction csrwi mtvec, 1?
  2. What is some_address? It must be properly aligned to a 4-byte boundary. Is it?
  3. In general, you can’t assume RISC-V registers are reset to 0. In your code, you are (I think) trying to globally enable interrupts in mstatus before configuring which interrupts you want to see in mie. If there was any junk in mip and mie registers, then you could get an interrupt that you weren’t expecting. I would swap the order of those two lines.
  4. What happens after you write the interrupt? Can you read back $mip register to see if the interrupt is pending?
  5. How do you know you aren’t taking the interrupt? Are you getting any sort of exception (perhaps just not the one you expect), or does the code just continue normally?
3

Hello,

  1. I wanted to enable vectored interrupts
  2. Yes, some address is 128 byte aligned, but it seems to me that there is no reason for this, since mtvec.mode is unavailable.
  3. Oh, it’s my mistake here, in real code they are in a proper sequence.
  4. The interrupt doesn’t occur immediately, but in mip I can see external and software interrupt pending. Though, now I can receive interrupts, and the cause register shows that this is an SWI. But I can’t understand now why it doesn’t occur right after writing 1 to 0x02000000 address. I run my code via debugger with stepi instructions.
  5. I should work on that further. I had an exception earlier, but now I am also receiving interrupts. So, I am going to figure out what’s happening in a few days.

Now, I know that vectored interrupts don’t work, so I will be able to work out my situation.
Thanks!

4

Ah, interrupts are disabled during stepi. That is probably the main cause of confusion.