Problems with CSR_MTVEC in Freedom Studio

HiFive1 Rev B
1

Hi everyone, I am making a timer interrupt for build a kernel, I was working directly with QEMU and my code worked, but now I want to work with Freedom Studio, because I bought a hifive rev-b, but still hasn’t arrived and right now I’m using Sifive GDB QUMU Debugging.

void system_init(){
	w_mepc((uint32_t)main);
	w_mtvec((uint32_t)switch_to);
	timer_init();
}

The problem is when I try to modify the “CSR MTVEC”, my code some times throws me this error “CSR_MTVEC: reserved mode not supported”.

I don’t understand why this happens, can someone explain it to me? and how can I correct it?

Thank you!

2

I did some research in the documentation and read that MTVEC has a bit of a mode to choose (I thought csr was just for address) as shown in the image below.

mtvec
mtvec965×212 29.6 KB

So when I write an address that ends with a number greater than two is when this error occurs, to solve it I used .align 2 in the subrutine. I hope this information can help someone.

Greetings

3

Hi @Juan_Romero nice to see you working with mtvec and mcause, they are very interesting.

The trap vector MODE bits, mtvec[1:0], determine whether the BASE, mtvec[31:2] is an absolute address, or a relative offset based also on the value of mcause (in relative mode, the “vector table” entries must be laid out on a four-byte boundary, of course).

The trap Exception Code (EC) bits, mcause[30:0], identify the particular kind of event that occurred. In the case of relative vectoring, this EC value is used as the index into the vector table.

The trap TYPE is the most significant bit of mcause; thus, a positive number (MSB=0) indicates an exception (events like breakpoints and access faults), while a negative number (MSB=1) indicates an interrupt (things like software, timer, and external events like those coming in from the PLIC). When using relative vectoring MODE, it is often quite handy to maintain two separate sets of trap handler vector tables, selectively determined by the TYPE of mcause.

Thus, when an interrupt occurs,
MODE=mtvec[1:0]=0 means that PC = mtvec[31:2]
MODE=mtvec[1:0]=1 means that PC = (mtvec[31:2] + 4 * mcause[30:0])

Section 3.1.15, and in particular Table 3.6, of Privileged Architecture Spec shows the various types of EC’s and their meanings.

I put together a brief example to help explain how to use mtvec and mcause. See the assembly code start.s (and its high-level C stub, main.c) in Demonstrating MTVEC

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4

You want a multiple of 4; a multiple of 2 will have the second bit set half the time and unset half the time. .align 2 is often the same as .p2align 2 though so works (i.e. it’s the same as .balign 4 since 4 is 2^2), just not in the way you say it does. I always suggest using .balign or .p2align explicitly though as .align varies in which it is between architectures and so can be extremely confusing.

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