Hi,
I was trying to understand reading code in /arch/riscv if mtvec is set for Vectored Mode.
Does anyone know it?
Hi,
I was trying to understand reading code in /arch/riscv if mtvec is set for Vectored Mode.
Does anyone know it?
Direct mode is used in Linux by setting mtvec.mode = 0.
Ok many thanks. I was not able to find the place where it was explicitly set.
So if I understand correctly here is the point where CLINT looks at mcause register
*static asmlinkage void riscv_intc_irq(struct pt_regs regs)
{
unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;*
if (unlikely(cause >= BITS_PER_LONG))*
panic("unexpected interrupt cause");*
switch (cause) {*
#ifdef CONFIG_SMP
case RV_IRQ_SOFT:*
/**
* We only use software interrupts to pass IPIs, so if a*
* non-SMP system gets one, then we don't know what to do.*
*/*
handle_IPI(regs);*
break;*
#endif
handle_domain_irq(intc_domain, cause, regs);*
break;*
and finally goes to PLIC to handle external interrupts
*static void plic_handle_irq(struct irq_desc desc)
{
struct plic_handler handler = this_cpu_ptr(&plic_handlers);
struct irq_chip chip = irq_desc_get_chip(desc);
void __iomem claim = handler->hart_base + CONTEXT_CLAIM;
irq_hw_number_t hwirq;*
WARN_ON_ONCE(!handler->present);*
chained_irq_enter(chip, desc);*
while ((hwirq = readl(claim))) {*
int irq = irq_find_mapping(handler->priv->irqdomain, hwirq);*
if (unlikely(irq <= 0))*
pr_warn_ratelimited("can't find mapping for hwirq %lu\n",*
hwirq);*
else*
generic_handle_irq(irq);*
}*
chained_irq_exit(chip, desc);*
}