First time poster.
I’ve used the search tool to look for answers to some of my questions, but I’ve not found what I’m looking for.
I’ve also submitted an email direct to Sifive, but not heard back.
Q1) Every photo I’ve seen of FE310 chips has had ‘ES’ on it.
From the datasheet:
"A fully qualified revision of this part in the same package and with a similar pinout
will be available in production quantities. Please consult with SiFive marketing for
schedule and specification."
a) Did FE310 ever complete qualification ?
b) What does the qual schedule look like?
Q2) Where do we buy FE310 chips ?
I know there was supposed to be a website:
But, I don’t see a link to buy chips, just to buy dev boards.
I’m sitting here reading “The RISC-V Reader” and the FE310 datasheet, side-by-side.
From the datasheet I’ve noticed that there are more GPIO than are exposed on the 48pin packaged chip.
It seems with the 48pin version, we loose access to a QSPI2, UART1, and QSPI1 is reduced to single bit mode, since the extra data pins don’t make it out.
Q3) In order to support all of the datasheet identified I/O, it appears to me that a 64pin chip would be needed.
a) Is there a follow-on, higher pin-count FE310 packaged part available ?
b) Is there a timeline for its release ?
I’m really enjoying the RISC-V Reader book, although I’m finding myself reading chapter 2 over and over to really come to grips with the RV32I integer instruction set. I hope the authors someday read Noam Nisan and Shimon Schocken, The Elements of Computing Systems. Also known as the NAND2Tetris Textbook. I find the manner in which Noam & Shimon depict the meaning of each bit, in each machine language instruction for their virtual RISC processor, to be more descriptive and perhaps more intuitive. Maybe that’s just me.
Q4) Final question, with all this processing power and large off-chip NOR / FRAM code space, the FE310 seems to me, to be short on SRAM. Is there a follow-on chip in the works with more on-chip SRAM, or a plan to make one of the QSPI peripherals serve as an addressable off-chip slow SRAM controller ?