The implication of atomicity of CSR instructions

Archive RISC-V
1

Hi, I am trying to implement the CSR operations and read in the spec that CSR[W|S|C] instructions should perform atomic Read-Modify-Write on CSRs.

My question is what the atomic here means? Is it from the perspective of single core or multi-core?

For example, if I am doing a classical 5-stage pipeline, can I read the values from CSR in the decode stage and do the set/clear in the execution stage (with possible forwarding logic)?

2

Answered in main RISC-V mailing lists, which is correct place to discuss general RISC-V questions and issues.