i am computer engineering student and have 1 year experience on RISCV. i have designed a 32IMC core, and now i am implementing CSRs in my core. but, i have one confusion that is in which pipeline stage i should place the CSR file, in memory stage as i saw in sodor and riscv-mini cores or in decode unit. also what will be the effect of both placements on performance.
guidance is much appreciated.