Learn from U500 platform spec, it says U500 platform has up to 8 x U5 app cores and optionally support one E5 MC. But what I see on VC7070 FPGA I am using now has only 4 cores (HART ID 0-3), and each of it supports GC ISA, S-mode and U-mode are supported as well on each core. Obviously, those cores are not E5 MC. Is this correct configuration of U500 VC707 FPGA? How can I have 8 U5 cores and E5 MC enabled on FPGA?
BTW, the mvendoris, marchid and mimpid all all 0, is this correct?
Thanks