Test and Debug Features

What hardware debug hooks does the FE310? JTAG-based register access? Triggers and traces? Cache and other memory dump?

Also, does the FE310 have full-scan testability? Will you give us access to that?

–Jason Doege

The FE310 implements version 11 of the RISC-V debug spec (https://dev.sifive.com/documentation/risc-v-external-debug-support-0-11/), which gives full visibility over JTAG into anything the processor can see (memory locations, peripherals, register file, etc). You can set HW and SW breakpoints on instruction or data. There is no trace support in the FE310.


Can I try RISC-V debug spec with C simulator rather than spike or devices(eg. FE310)?

I found that riscv-tests/debug demonstrates how to debug these target (spike32/64, fe300 and fu500). Can I debug C simulator target (emulator-rocketchip-DefaultConfig) with openOCD( JTAG ) as target fe300/fu500 do so?

This works with the VCS simulator. It uses the jtag_VPI to interface with OpenOCD.

To get the simv that includes the JTAG VPI, you have to prepend “WithJtagDTM_” to your CONFIG:

make CONFIG=WithJtagDTM_DefaultConfig

Once you have the simv, eg simv-rocketchip-WithJtagDTM_DefaultConfig, you can use the riscv-tests/debug flow to use the ‘sim’ version.

I believe because this depends on VPI, it doesn’t work with the emulator, just VCS, but I haven’t tried using the emulator with it in a while.

Let me know if that’s not clear.

@mwachs5 Thinks very much! I would have a try.