Simulate JTAG debugging interface

I would like to simulate the JTAG debugging interface of freedom-e300 with VCS.

In freedom/src/main/scala/everywhere/e300artydevkit/Config.scala I noticed that the WithJtagDTM has been added into the configuation (, so the synthesized verilog has debugTransportModuleJTAG. Is there a script to simulate this interface already?

If not, how do I proceed it in general?

The basic idea is that you launch your simulation with +jtag_vpi_enable, then connect OpenOCD to it and debug to your heart’s content.

Check out this thread, Forum user @kimokono did a great job writing up what they did:

Or, you can check out this rocket-chip PR for reference:

The same basic approach will work for simv compiled in Freedom.

Sure, I will give it a try and let you know if I have any question. Thanks @mwachs5 :slight_smile:

BTW, will this work if a different simulator is used (e.g. NCSim, Modelsim)? How do we incorporate this flag jtag_vpi_enable with different simulators?

My rocket-chip PR is to get it to work with Verilator (the open source simulator). I haven’t tried with the other simulators. The +jtag_vpi_enable is read by the internal Verilog code, it’s not intrinsic to the simulator.

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By default, the config in freedom-e300 should include JtagDTM, so I just make verilog, but I didn’t see JTAG VPI module in the synthesised verilog though?

Right, that would have to be in your TestHarness code.

Sure, I followed the thread you put above, but it seems like after I saw the meesage:

“connection to suceed”, it stucks at the message:

“Debug: 177 7 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset”

Did I do anything wrong?