Simulate JTAG debugging interface

Archive Freedom E300
1

I would like to simulate the JTAG debugging interface of freedom-e300 with VCS.

In freedom/src/main/scala/everywhere/e300artydevkit/Config.scala I noticed that the WithJtagDTM has been added into the configuation (https://github.com/sifive/freedom/blob/master/src/main/scala/everywhere/e300artydevkit/Config.scala#L23), so the synthesized verilog has debugTransportModuleJTAG. Is there a script to simulate this interface already?

If not, how do I proceed it in general?

2

The basic idea is that you launch your simulation with +jtag_vpi_enable, then connect OpenOCD to it and debug to your heartā€™s content.

Check out this thread, Forum user @kimokono did a great job writing up what they did:

Or, you can check out this rocket-chip PR for reference:

The same basic approach will work for simv compiled in Freedom.

3

Sure, I will give it a try and let you know if I have any question. Thanks @mwachs5 :slight_smile:

BTW, will this work if a different simulator is used (e.g. NCSim, Modelsim)? How do we incorporate this flag jtag_vpi_enable with different simulators?

4

My rocket-chip PR is to get it to work with Verilator (the open source simulator). I havenā€™t tried with the other simulators. The +jtag_vpi_enable is read by the internal Verilog code, itā€™s not intrinsic to the simulator.

1 Like
5

By default, the config in freedom-e300 should include JtagDTM, so I just make verilog, but I didnā€™t see JTAG VPI module in the synthesised verilog though?

6

Right, that would have to be in your TestHarness code.

7

Sure, I followed the thread you put above, but it seems like after I saw the meesage:

ā€œconnection to 127.0.0.1:52484 suceedā€, it stucks at the message:

ā€œDebug: 177 7 core.c:327 jtag_call_event_callbacks(): jtag event: TAP resetā€

Did I do anything wrong?