Spi 1

HiFive Premier P550
1

Hi, I have some problems when trying to use the SPI of HiFive Premier P550 (EIC7700X), I didn’t find any device related to spidev in the system, then I recompiled the kernel (the kernel version used is GitHub - sifiveinc/riscv-linux at rel/kernel/hifive-premier-p550) and turned on CONFIG_SPI_SPIDEV, and then also enabled ssi1 in the device tree.

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ssi1: spi@50814000 {
	compatible = "snps,eic7700-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x50814000 0x0 0x4000>;
	spi-max-frequency = <4800000>;
	clocks = <&d0_clock EIC7700_CLK_LSP_SSI1_PCLK>;
	clock-names = "clk";
	interrupt-parent = <&plic0>;
	interrupts = <92>;
	resets = <&d0_reset SSI_RST_CTRL SW_SSI_RST_N_1>;
	reset-names = "spi";
	eswin,spi_dma = <&d0_aon_dmac>;
	dmas = <&d0_aon_dmac 36 4>, <&d0_aon_dmac 37 4>;
	dma-names = "rx", "tx";
	status = "disabled";
};

pinctrl_spi1_default: spi1-default{
	mux{
		groups = "spi1_group";
		function = "spi1_func";
	};
};

&ssi1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi1_default>;
	num-cs = <1>;
	cs-gpios = <&porta 35 GPIO_ACTIVE_LOW>;
	
	spidev1: spidev@0 {
		compatible = "spidev";
		reg = <0>;
		spi-max-frequency = <4800000>;
	};
};

But after completing the above work, there is still no way to use spidev, then I found compatible = "snps,eic7700-spi";. I want to know which driver is responsible for the SPI controller snps,eic7700-spi, and I can’t find any information related to this keyword in the kernel source code.

I am not familiar with device-tree, and I would like to know if there is anything wrong with the steps above? How can I connect peripherals using the SPI interface on the P550?

3

hi user,
can we know on which pins you have connected SPI peripherals ?

thanks.

4

It seems that SiFive’s linux kernel didn’t port the ESWIN’s patch over. In ESWIN’s linux tree, there’s the support for SPI:

And later ESWIN disabled DMA capability for the SPI controller:

So looks like it’s essentially a dw-spi device, and no ESWIN quirks (which is good). Without recompiling the kernel, you can try to hack the device-tree by changing the compatible string to snps,dw-apb-ssi. However this does enable the DMA capability. I suspect the reason behind ESWIN’s second patch is because all the DMA of the SoC are not cache-coherent, so perhaps they found some issues enabling it? Not sure. Anyway, good luck.

1 Like
5

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I used these pins.

6

Thank you very much, this is very helpful. :grinning_face:

7

Hi @fetch150zy ,
These pins are configured as GPIO in current release. For the compatible string @ganboing has already shown some guide which is correct. We are validating it by pinmux changes to use those pins as SPI and validate with one SPI slave device. Once we validate we can share confirm changes. It seems that you have some progress based on @ganboing suggestions. So, once we have some results of SPI slave testing, we can share changes to validate SPI.

Thanks.

8

Hi, you can refer to the following modifications for the SPI configuration and conduct tests on the SPI flash.

diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
index e4fc03166..0aabbd7f3 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -565,8 +565,21 @@
 };
 
 &ssi0 {
-	/* pin header mux with GPIO 35,36,37,38,39,40 */
-	status = "disabled";
+	/* pin header mux with GPIO 35,36,37,38,39,40 41*/
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spi1_default>;
+	/* spi flash */
+	num-cs = <1>;
+	spi-flash@0 {
+		compatible = "winbond,w25q128fw",
+					"jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <4800000>;
+		rx-sample-delay-ns = <10>;
+	};
 };
 
 &ssi1 {
@@ -821,16 +834,14 @@
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpio6_default &pinctrl_gpio7_default &pinctrl_gpio8_default &pinctrl_gpio9_default
-			&pinctrl_gpio10_default &pinctrl_gpio17_default &pinctrl_gpio35_default &pinctrl_gpio36_default
-			&pinctrl_gpio37_default &pinctrl_gpio38_default &pinctrl_gpio39_default &pinctrl_gpio40_default
-			&pinctrl_gpio41_default &pinctrl_gpio46_default &pinctrl_gpio52_default
-			&pinctrl_gpio53_default &pinctrl_gpio64_default &pinctrl_gpio65_default &pinctrl_gpio66_default
-			&pinctrl_gpio67_default &pinctrl_gpio70_default &pinctrl_gpio73_default &pinctrl_gpio83_default
-			&pinctrl_gpio86_default &pinctrl_gpio87_default &pinctrl_gpio92_default &pinctrl_gpio93_default
+			&pinctrl_gpio10_default &pinctrl_gpio17_default &pinctrl_gpio46_default	&pinctrl_gpio52_default
+			&pinctrl_gpio53_default	&pinctrl_gpio64_default &pinctrl_gpio65_default &pinctrl_gpio66_default
+			&pinctrl_gpio67_default	&pinctrl_gpio70_default &pinctrl_gpio73_default &pinctrl_gpio83_default
+			&pinctrl_gpio86_default	&pinctrl_gpio87_default &pinctrl_gpio92_default &pinctrl_gpio93_default
 			&pinctrl_gpio94_default>;
 
     /* pin header default function for GPIO
-       SPI1 (CS0,SCLK,MOSI,MISO,D2,D3): GPIO 35,36,37,38,39,40
+       SSI0 (CS0,SCLK,MOSI,MISO,D2,D3,CS1): GPIO 35,36,37,38,39,40,41
        I2C1 (SCL,SDA): GPIO 46,47
        UART3(TX,RX): GPIO 92,93
     */