[solved] Spike - Machine Timer Registers (mtime and mtimecmp)

Does anyone know if the spike simulator provides any machine timer support? If so, what is the memory mapping for the registers mtime and mtimecmp?

These memory mapped registers are specified in Privileged Architecture Version 1.10 - 3.1.15
Machine Timer Registers (mtime and mtimecmp)


Note for future readers: Yes, Spike provides timer simulation.

see https://github.com/riscv/riscv-isa-sim/issues/205

I couldn’t find any documentation for these “platform” features. However, a cursory grep of this repo shows these memory mapped registers are defined in ./riscv/clint.cc

/* 0000 msip hart 0
 * 0004 msip hart 1
 * 4000 mtimecmp hart 0 lo
 * 4004 mtimecmp hart 0 hi
 * 4008 mtimecmp hart 1 lo
 * 400c mtimecmp hart 1 hi
 * bff8 mtime lo
 * bffc mtime hi

#define MSIP_BASE	0x0
#define MTIMECMP_BASE	0x4000
#define MTIME_BASE	0xbff8