Disabling timer counting on Hifive1 reb B

Is there any way to disable counting on the mtime timer register?
from the FE310-G002 manual “mtime is a 64-bit read-write register that contains the number of cycles counted from the rtcclk input…”. Is there a way to disable that input?

I am not sure, but mtime is writable, so you could manually reset it to 0 or a arbitrary time as well (and if you were depending on interrupts, you could suspend those until you do reset the register).

I’m thinking maybe

  1. Disable timer interrupt
  2. Read and save off current mtime
  3. Write saved value back to mtime
  4. Restore interrupts (may need a special case if mtimecmp is only a few ticks away from mtime)

If that is what you need. What did you need the timer suspend for, if you don’t mind sharing?

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Thank you for your response :smiley:
I just want to suspend the timer and re-enable it without having to disable interrupts every time . but since its not possible I think I will just store mtime, reset it and put mtimecmp to max to avoid interrupts and restore values when needed.

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Of course! Glad to help.

And totally understand as touching mtimecmp or mtime here involves multiple instructions for the 64-bit wide register…

It’s possible there’s an undocumented mux here, but nothing is jumping out at me skimming the sifive-blocks source :slight_smile:

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