Simulate JTAG debugging interface

mwachs5 · December 6, 2017, 5:52pm

The basic idea is that you launch your simulation with +jtag_vpi_enable, then connect OpenOCD to it and debug to your heart’s content.

Check out this thread, Forum user @kimokono did a great job writing up what they did:

Or, you can check out this rocket-chip PR for reference:

github.com/chipsalliance/rocket-chip

[WIP] Add Debug Tests to Regression

chipsalliance:master ← chipsalliance:new_remote_bitbang

opened 03:33PM - 03 Nov 17 UTC

mwachs5

+735 -102

This adds a single test from riscv-tools/riscv-tests/debug to our rocket chip re…gressions, for both a 32 and 64-bit core. So far it is working but not always passing. To run (`DEBUG=1` is optional) ``` cd regression make vsim-jtag-dtm-regression SUITE=JtagDtmSuite DEBUG=1 ``` To use Verilator: ``` cd regression make emulator-jtag-dtm-regression SUITE=JtagDtmSuite DEBUG=1 ``` I still need to stabilize it and make it deterministic (as the JTAG VPI version is) such that time does not advance in the simulation until each OpenOCD packet is received. Both Verilator and VCS sims are supported. In order to run with verilator, this PR replaces the JTAG VPI with a SimJTAG which understands OpenOCD's "Remote Bitbang" protocol. This is similar to what is used in Spike. I have left the JTAG VPI in place, but this repo no longer uses it. @timsifive FYI.

The same basic approach will work for simv compiled in Freedom.

Topic		Replies	Views
VCS simulation infinite loop with JTAG VPI Freedom E300	15	7268	November 21, 2017
Test and Debug Features Freedom E300	4	3309	December 20, 2016
Jtag debug problem RISC-V	3	2823	September 18, 2019
Unsupported DTM Version Freedom E300	16	55472	June 7, 2019
Using vcs tool to simulate rocket-chip failure through jtag General	0	2809	June 30, 2020

Simulate JTAG debugging interface

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