Rocket core - data memory connections


Is there any document on how the rocket core accesses the data memory (dcache / scratchpad)? I am working on adding a router between the core and the memory. There are certain parameters which I couldn’t fully understand yet. (I am using the rocket chip generator that is within the fpga-zynq repo).

I hope this is the right place for this issue.


If you mean then that’s Berkeley university and nothing to do with SiFive (though some SiFive people of course studied at Berkeley).

At the moment the only FPGA boards SiFive supports (for our own cores) and has experience with are the original Arty (35T) and VC707.