[RISC-V Full System Simulator] MARSS-RISCV: Micro-ARchitectural Full System Simulator for RISC-V

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Hi,

The CAPS Research Group at SUNY-Binghamton (Binghamton University) announces the availability of MARSS-RISCV: Micro-ARchitectural System Simulator for RISC-V , a true full system, cycle-accurate simulator for RISC-V processors built upon TinyEMU by Fabrice Bellard and uses its code for all the device emulation and configuration. MARSS-RISCV can simulate the execution of applications, OS (including system calls), libraries, interrupt handlers and boot loaders, cycle-by-cycle on pipelined implementations.
Some of the features of MARSS-RISCV include:

  • True full system simulation: simulates in a cycle-accurate fashion the execution of instructions in the entire software stack including the boot-loader, system calls and OS code, libraries, interrupt handlers, user level applications etc.
  • Fully configurable, cycle-accurate, in-order and out-of-order single-core RISC-V CPU with support for:
    • RV32GC and RV64GC (user level ISA version 2.2, privileged architecture version 1.10)
    • Multiple execution units with configurable latencies (execution units can be configured to be pipelined)
    • 2-level cache hierarchy with various allocation and miss handling policies
    • A simple DRAM model that accounts for open-page hits
    • A variety of branch predictors: bi-modal and 2-level adaptive (Gshare, Gselect, GAg, GAp, PAg, PAp)
  • Supports VirtIO console, network, block device, input and 9P filesystem.
  • MARRS-RISCV is easy to install, use and modify and uses a JSON configuration file

The simulator is currently in alpha status as we are validating the cycle accuracy using various development boards. The development of MARRS-RISCV is supported in part by the DARPA SSITH program.

For more information, please visit: https://github.com/bucaps/marss-riscv

We look forward to the valuable feedback from the RISC-V community and potential users.

Regards & Thanks,
CAPS Team

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