Question about RISC-V software interrupt

I’m switching from ARM to RISC-V, still learning RISC-V. With ARM GiC, there are 16 software interrupt IDs (0~15). So Core A can send SGIs (Software Generated Interrupts) to Core B with different IDs to indicate the intention of the interrupt, such that B can handle it accordingly.
But in RISC-V, to my understanding, it has only one software interrupt ID (which is 3 in M mode, assuming I run M mode only). How do I implement the similar logic as described above in RISC-V?