Question about RISC-V software interrupt

I’m switching from ARM to RISC-V, still learning RISC-V. With ARM GiC, there are 16 software interrupt IDs (0~15). So Core A can send SGIs (Software Generated Interrupts) to Core B with different IDs to indicate the intention of the interrupt, such that B can handle it accordingly.
But in RISC-V, to my understanding, it has only one software interrupt ID (which is 3 in M mode, assuming I run M mode only). How do I implement the similar logic as described above in RISC-V?


Hi Huang,
In ARM how you are achieved software interrupts between two cores virtually?
Is this done via in a QEMU platform ?
Please share resources on that
Thank you

@oscarh You may check the RISC-V Advanced Interrupt Architecture (AIA) document that supports Message-signaled interrupts (MSIs) and Inter-processor Interrupts(IPIs)

In ARM, we achieve IPI by writing a GIC (Generic Interrupt Controller) register with the interrupt ID, which can be any number between 0 and 15 (inclusive), and the ID of the core to be interrupted.


Thanks for your reply Oscarh.
I will look into that.