Using Software Interrupts in RISC-V

Archive RISC-V
1

Hello,
I’m trying to understand interruption operations (especially Timer Interrupts and Software Interrupts IPIs) by studying riscv-pk source code and simulating my software against Spike -p4 and Emulator (generated using verilator).

I succeeded to launch Timer interrupts using SBI calls provided in pk (cf. riscv-pk/machine/mtrap.c) and then handle them (cf. riscv-pk/pk/handlers.c).

I still don’t know what’s wrong with IPIs. My understanding is that they need to be initiated from M-mode, therefore we need to use SBI (SBI_SEND_IPI), but:

– When I do this in Spike (-p4), I get “Load address misaligned”:
machine mode: unhandlable trap mcause=0000000000000004

– When I test it in emulator (with DefaultConfig both with a mono- and multi- core configuration)

    [ handle_trap ]     cause=0000000000000005
    z  0000000000000000 ra 00000000800029a2 sp 000000008000de60 gp 0000000000000000
    tp 0000000000000000 t0 0000000000000025 t1 0000000000000000 t2 0000000000000009
    s0 0000000000000000 s1 00000000800150e0 a0 000000000000000e a1 000000008000c85c
    a2 000000008000c864 a3 ffffffffffffffff a4 0000000000000000 a5 00000000800148a4
    a6 0000000000000000 a7 0000000000000004 s2 0000000000000000 s3 0000000000000000
    s4 0000000000000000 s5 0000000000000000 s6 0000000000000000 s7 0000000000000000
    s8 0000000000000000 s9 0000000000000000 sA 0000000000000000 sB 0000000000000000
    t3 0000000080015010 t4 ffffffffffffffff t5 fffffffffffffffc t6 0000000000000015
    pc 00000000800029aa va 000000000000000e insn       ffffffff sr 8000000200046120
    Load access fault!

Questions:

  • Why do I get different exceptions between Spike and the [C++] Emulator ?
  • Any pointers to a detailed or an example of IPIs usage/implementation flow?

Thank you very much.