Plic and InterruptBus

Has anyone studied the language of Plic.scala? I have a doubt that “import freechips.rocketchip.coreplex. {HasInterruptBus, HasPeripheryBus}”. Can anyone tell me about HasInterruptBus functionality and interface? Thanks!

These are Scala traits. A Module which HasInterruptBus has an interrupt bus variable named ibus which the PLIC will be able to hook up to (since it is an interrupt source). Similarly, HasPeripheryBus means that there will be a periphery bus variable named pbus which the PLIC will be able to hook up to, like many peripheral devices that the CPU accesses with memory-mapped accesses.

Therefore, any Module (e.g. a Core Complex) which HasPeripheryBus and HasInterruptBus will be able to include a PLIC:



:smiley:Thank you for your reply. Sorry, it’s a bit late to reply you because something is a bit lately. Interruptbus and PLic, their contact I probably understand, but can not find the specific description in the RV corresponding documentation (for example, riscv-privileged-v1.10).I want to know their docking operations, which is very helpful for me to understand their scala language

I’m not quite sure what you are asking, but you can find pretty good documentation for how the PLIC in rocket-chip actually is implemented/how to interact with it in the SiFive Core IP Manuals: