The plic defaults to level interrupt.I saw in the manual that plic can handle pulse interrupts.But I don’t find register associated with it.
Do you mean interrupts coming from GPIO pins? Which hardware? You posted this to RISC-V, but AFAIK, how external signals are converted to interrupts is platform dependent.
My core is generated from rocket-chip.I have not made any changes to the files related to plic.In this manual riscv-privileged-v1.10.pdf
there is a description of how to handle level-triggered interrupt and edge-triggered interrupt.But I don’t find register associated with it.
