I’m looking for the specification for the platform-level interrupt controller used in the Premier P550. Specifically, I’m looking for how it organizes the different interrupt contexts (which hart and privilege modes map to which contexts). I’m looking to enable the usb0 interrupts for the s-mode of the boot hart.
I don’t think EIC7700’s PLIC is that different. From the TRM, it’s just like any standard PLIC that can route any global interrupt to M or S mode of a given hart or a set of harts (although only one can claim that interrupt, so usually there’s no point interrupting multiple harts). Just enable the corresponding interrupt in the S mode context of the designated hart, and that’s it.
But I don’t know which context corresponds to the s-mode of the given hart. The RISC-V PLIC standard leaves the organization of the contexts to be specified in the manufacturer’s specification, which I could not find.
Refer to
https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases/download/v1.0.0-20250103/EIC7700X_SoC_Technical_Reference_Manual_Part1.pdf
Chapter 3.4.1.12
That’s it! Thanks a ton!
Until just now, I had missed the one-byte unique, and arguably incompatible, “PLIC global clock gating disable feature” at 0x0C1F_F000. It’s set to 1 at reset and has to be set to zero for the PLIC to function. (Or not, the double negatives in the manual don’t help.)
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This bit does not need to be set for the PLIC to function. It only controls an (optional, but recommended) autonomous clock gating feature. You can see in the upstream Linux bringup (Making sure you're not a bot!) and the BSP OpenSBI (meta-sifive/recipes-bsp/opensbi/opensbi-sifive-hf-prem at rel/meta-sifive/hifive-premier-p550 · sifiveinc/meta-sifive · GitHub) that there is no special software for this variant of the PLIC.
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