@HEX-Five, apologies if this isn’t the right channel to reach you on, but I saw another post from you on this forum, and anyway have a deeper SiFive related question.
I want to experiment with your MultiZone solution - I’m looking at building an isolated TCP/IP application with one zone dedicated to the stack (picoTCP, lwIP or the likes) and another zone serving as my application. i.e. you can compare this somewhat to the Sidecar pattern containerization approach. My hope is that I can abstract away the TCP/IP both for security isolation and ease of use and porting.
Now, since I’m new to this, apologies if I’m asking any dumb questions, but I’m having issues grasping E31, E300 and which of these MultiZone targets and runs on. Could you shed some light as to the specific requirements? I’m clear that you need PMP, but not too clear on memory and processor speed requirements.
Also, maybe someone from SiFive watching this could also help to clarify the differences between the two. I’ve built my own E300 from sifive/freedom and deployed just the bitstream to the Arty board after I had flashed the E31 mcs file I downloaded from SiFive Developers some time ago. The LEDs are still flashing, but I needed to change the openocd expected IDCODE and the UART baudrate. I’ve done a bit of investigation and have compiled a (non-exhaustive) list of differences that I’ve added below. My sources are basically the generated DTS, sifive/freedom sources and a SiFive E31 Core Complex Manual v2p0 that I found online.
# General
E31 | E300
----------------------------------------------------+-------------------------------------------------------------
JTAG ID 0x10e31913 | 0x20000913
Clock 65 MHz | 32.5 MHz
PMP Implemented | Implemented
I-Cache 64 sets, 2-way | 64 sets, 1-way
D-Cache 1024 sets, 1-way | 256 sets, 1-way
# Address map
E31 | E300
----------------------------------------------------+-------------------------------------------------------------
Base Top Attributes Description | Base Top Attributes dts name/Description
0x0000_0000 0x0000_00FF Reserved | 0x0000_0000 0x0000_1000 RWX A debug-controller
0x0000_0100 0x0000_0FFF RWX A Debug |
0x0000_1000 0x01FF_FFFF Reserved | 0x0000_3000 0x0000_4000 RWX A error-device
| 0x0001_0000 0x0001_2000 R X rom (BootROM)
0x0200_0000 0x0200_FFFF RW A CLINT | 0x0200_0000 0x0200_FFFF RW A clint
0x0201_0000 0x07FF_FFFF Reserved | cpu i-cache-size (4 KiB)
0x0800_0000 0x0800_1FFF RWX A ITIM (8 KiB) |
0x0800_2000 0x0BFF_FFFF Reserved |
0x0C00_0000 0x0FFF_FFFF RW A PLIC | 0x0C00_0000 0x0FFF_FFFF RW A interrupt-controller
0x1000_0000 0x1FFF_FFFF Reserved | 0x1000_0000 0x1000_0FFF RW A aon
| 0x1001_2000 0x1001_2FFF RW A gpio
| 0x1001_3000 0x1001_3FFF RW A serial
| 0x1001_4000 0x1001_4FFF RW A spi
| 0x1001_5000 0x1001_5FFF RW A pwm
| 0x1001_6000 0x1001_6FFF RW A i2c
| 0x1002_3000 0x1002_3FFF RW A serial
| 0x1002_4000 0x1002_4FFF RW A spi
| 0x1002_5000 0x1002_5FFF RW A pwm
| 0x1003_4000 0x1003_4FFF RW A spi
| 0x1003_5000 0x1003_5FFF RW A pwm
0x2000_0000 0x3FFF_FFFF RWX A Peripheral Port | 0x2000_0000 0x3FFF_FFFF R X spi
0x4000_0000 0x5FFF_FFFF RWX System Port |
0x8000_0000 0x8000_FFFF RWX A DTIM | 0x8000_0000 0x8000_3FFF RWX A dtim
0x8001_0000 0xFFFF_FFFF Reserved |
#Functionality (with the SiFive demo program in flash)
----------------------------------------------------+-------------------------------------------------------------
UART Baud 115200 | 57600
#Functional testing
----------------------------------------------------+-------------------------------------------------------------
JTAG Works | Works
UART Baud Works | Works
LED blink Works | Works
Timer Works | Works
Timer Works | Works