Chapter 5 states the four values of
0 0 trap loop
0 1 j QSPI (0x2000 0000)
1 0 j OTP (0x0002 0000)
1 1 j ROM (0x0001 0000) (on -G000 it’s 0x00001000 or a typo?)
Since we observe normal start up from the qspi flash device, it must be the case that MSEL is pulled high, and MSEL is either pulled low or floats to low level.
Looking at the schematic of HiFive1 Rev B there is a pullup resistor R29 (100k) on physical pin 1. Pin 1 is GPIO-31, also SPI2-DQ3 (aka, QSPI-DQ3). It would make sense for the initial boot select pins to be grouped together with the external device that reads at boot, and placed sequentially at either the high end or the low end of physical pins and/or i/o lines.
If I had to fathom a guess, the two (and possibly all four) MSEL pins are
MSEL-0 GPIO-31 48QFN-pin-1
MSEL-1 GPIO-30 48QFN-pin-2
MSEL-2 GPIO-28 48QFN-pin-3
MSEL-3 GPIO-27 48QFN-pin-4
The Preliminary Datasheets, for both -G000 and -G002 parts, has a typo in Figure2.1; there are duplicate “QSPI-DQ-2’s” and two pin 2’s.
There is a slightly different description of the boot chapter in the Manual for the -G000 part. There, it makes reference to three signals
psdqspien, instead of the two
HiFive1 Rev B Schematic