Initial OTP programming of FE310-g002 chips

hello @camdenmil your findings are very interesting. some time ago @tincman and I were discussing a similar question, here
msel-pins-on-fe310

it would really be nice to find where is the external hardwired control of MSEL; my best guess is in the discussion at the link above.

also, note the minor difference between -g000 and -g002:
Chapter 5 of the User Manual states the four values of MSEL[1:0] are
MSEL[1:0]
0 0 trap loop
0 1 jump to QSPI (0x2000 0000)
1 0 jump to OTP (0x0002 0000)
1 1 jump to ROM (0x0001 0000) (on -G000 it’s 0x00001000, not a typo)