I’m working on an Unleashed configuration of Freedom auto generated from chisel. I’m having an issue with clk syncing in the design. The clk flows as described below:
- Top level generates JTAG clk.
- Various clks enter the Debug module (DM) all but the JTAG has a sync by default.
- Output named “ndmreset” going to core (via OR gate). But this signal isn’t synced to sys_clk and is still under jtag_clk freq.
I’m guessing this is a mistake.
As I generated another clk for the system I"m desinging, I’m having trouble with the JTAG clk not being synced.
Is there something I’m missing?
Shouldn’t there be a sync to the general sys_clk on this signal as well (like all other DM clk syncs)?