Is CLIC (Core Local interrupt Controller) RISC-V Compliant?

Hi to you all,
I’m working to upgrade the CV32E40P core interrupt system. I already implemented a CLINT (core local interrupter) and I’m now considering CLIC.

Looking at SiFive documentation SiFive Interrupt Cookbook, on page 18:

[CLIC] Extends themodefield ofmtvecby six bits, [5:0], where [1:0] are defined to support two additional modes: CLIC directand CLIC vectored.

Now, from the privileged specs by the foundation (table 3.5), what I understood is that a maximum of 2 modes can be officially encoded in mtvec: Direct and Vectored mode. Also, extending the mode field will result in different alignment constraints for the base address.
So my question, is CLIC compliant with the specs? I would say no, but maybe I misunderstood either the specs or the SiFive manual.

I noticed that interrupt are vectored trough the non-standard mtvt, so that mtvec is base only for exception. Also, mtvt is placed at address 0x307, which in the specs (table 2.1) it said to be usable for standard only csrs. This reinforces my convinction that CLIC is not risc-v compliant, but I would be pleased to be corrected.


CLIC is an evolving draft, there is no official spec yet. See
CLIC changes the interpretation of the mtvec register. When the clic spec is finished and official, the other docs will be updated to be compatible with it.

SiFive has an implementation of an earlier draft, so the SiFive implementation and docs may not be identical to the current evolving draft.

1 Like

Thanks, was about to reply to my own question.
Apparently the CLINT-CLIC-PLIC triplete was not clear to me, now it is a bit more.
For my design I just implemented what is said in the specs, but I see that CLIC proved a lot more flexibility at expense of area/complexity of course.