E21 CLIC Interrupt Mapping?

Archive SiFive RISC-V Core IP Evaluation
1

Is there a complete list of interrupts for the E21 CLIC running on the Arty-A7 FPGA? coreip-arty-userguide-v3p0.pdf includes some information about the interrupt numbers, but it isn’t very clear.

This is what I’ve seen so far:

3  - msip
7  - mtip
11 - meip
12 - csip
16 - gpio[0]
17 - gpio[1]
18 - gpio[2]
19 - gpio[3]
20 - gpio[4]
21 - gpio[5]
22 - gpio[6]
23 - gpio[7]
24 - gpio[8]
25 - gpio[9]
26 - gpio[10]
27 - gpio[11]
28 - gpio[12]
29 - gpio[13]
30 - gpio[14]
31 - gpio[15]
32 - uart

And then maybe, I’m not really sure:

46 - button[0]

Does someone have a definitive list with indices that match up with the addresses in the CLIC registers?

2

Some related information that I remember now:

List of Interrupts in the E21 Core
SiFive E21 Core Complex Manual v19.02
Table 10: mcause Exception Codes

How GPIO match to board elements and interrupts
SiFive Core IP FPGA Eval Kit User Guide v3p0
Table 7.1: Core IP FPGA Eval Kit GPIO Offset to Board Pin Number
Table 7.2: Core IP FPGA Eval Kit Local Interrupts Mapping

An example of CLIC handling button interrupts

3

Table 7.2 is certainly very useful (albeit confusing because those are not local interrupt numbers, those are the numbers from the base of the CLIC, and the clarification about mie is just more confusing since the CLIC doesn’t use mie), but how should I use table 7.1? What is a global interrupt on the E21 core? What do those numbers correspond to?

Unfortunately tracking through the old clic-vectored code (which I’m hoping to save future developers from having to do) just shows that the button indices match table 7.2.

We really just need a simple table of how the interrupts are wired in the E21 core.