Hello
the processor support I/O Space？If so，what is I/O base address？
For what? There are many memory-mapped peripherals, each with their own address range in the address space, and if you mean PCIe I/O space then the PCIe controller has a memory-mapped address range that gets translated to that. All should be documented in the manual.
I don’t think it is though; sadly the DesignWare PCIe host bridge IP is proprietary and not documented at all. According to the Linux device tree file for FU740-C000 the PCIe I/O decode window is at 0x60080000-0x6008ffff. I have no idea if that is hardwired or programmable.
Hm, that’s true, the FU740 manual just gives a few large address ranges for “PCIe”. But the device tree indeed tells you what the address range is for its memory-mapped I/O space translation. I’d be surprised if it’s programmable.
I want to execute x86 option ROMs on risc-v architecture, but the option ROMs internally involve some VGA I/O ports (such as 0x3C0, 0x3C3) that need to be mapped to the I/O space on the processor
Well, where the GPU’s I/O space is mapped within the PCIe controllers I/O translation region will depend on how the firmware configured the I/O bars.